1. Field of the Invention
The present invention relates to a non-volatile memory integrated circuit device and a method of fabricating the same and, more particularly, to a non-volatile memory integrated circuit device and a method of fabricating the device, in which the amount of on-cell current during a read operation is increased.
2. Description of the Related Art
Non-volatile memory integrated circuit devices used in contactless smart cards, such as a credit card, an Identification (ID) card and a bank entry card, require high reliability, a short access time and low power consumption. Conventional non-volatile memory integrated circuit devices do not meet these requirements. For example, a flash memory cell having a NOR architecture employs Channel Hot Electron Injection (CHEI) at the time of programming and employs Fowler-Nordheim (FN) tunneling at the time of erasing, resulting in an over-erasing problem. Furthermore, a flash memory cell having a NAND architecture employs FN tunneling both at the time of programming and at the time of erasing, and thus requires a significantly high voltage.
To overcome these problems, a flash memory cell having two transistors (hereinafter referred to as a “2Tr flash memory cell”) has been developed. In more detail, the 2Tr flash memory cell includes a memory transistor and a select transistor, which are connected in series. The memory transistor is connected to a bit line and the select transistor is connected to a common source. A floating junction is disposed between the memory transistor and the select transistor.
The 2Tr flash memory cell has a very short access time because it employs an NOR architecture. Furthermore, the over-erasing problem does not occur in the 2Tr flash memory cell because the select transistor is used. In addition, since program and erase operations are performed using FN tunneling, the current (or power) required at the time of programming or erasing can be reduced and high efficiency can be achieved using low voltage.